Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP4083147
Kind Code:
B2
Abstract:
A semiconductor memory device having a virtual ground line type memory array structure includes a readout circuit for selecting a pair of selected bit lines connected to the source and the drain of a memory cell to be read, applying a predetermined voltage to between the paired selected bit lines, and sensing a memory cell current flowing through the memory cell to be read, and a counter potential generation circuit for generating from an intermediate node potential, which is higher than any level of the potential on the selected bit lines and supplied from an intermediate node on a current path for feeding the memory cell current in the readout circuit, a counter potential which varies in the same direction as of the intermediate node potential depending on the memory cell current so that its variation is greater than that of the intermediate node potential, wherein the counter potential is applied to an unselected bit line allocated next to one at a high level of the paired selected bit lines.
Inventors:
Kaoru Yamamoto
Nobuhiko Ito
Yoshimitsu Yamauchi
Nobuhiko Ito
Yoshimitsu Yamauchi
Application Number:
JP2004197007A
Publication Date:
April 30, 2008
Filing Date:
July 02, 2004
Export Citation:
Assignee:
Sharp Corporation
International Classes:
G11C16/04; G11C16/06
Domestic Patent References:
| JP2006520515A | ||||
| JP6020488A | ||||
| JP2003281896A | ||||
| JP2003323796A | ||||
| JP3176895A |
Attorney, Agent or Firm:
Yoshifumi Masaki