Title:
PLL回路
Document Type and Number:
Japanese Patent JP4094851
Kind Code:
B2
Abstract:
A PLL circuit having a gain control function includes: a first phase comparator for outputting a first phase difference signal indicating a phase difference between a first input signal and a second input signal; a first loop filter for smoothing a signal based on the first phase difference signal and outputting a first control voltage; a VCO for oscillating at a frequency based on the first control voltage and thereby outputting a first clock; and a dummy VCO having characteristics identical with those of the VCO for oscillating at a frequency based on a second control voltage and thereby outputting a second clock.
Inventors:
Seiichi Ozawa
Application Number:
JP2001553665A
Publication Date:
June 04, 2008
Filing Date:
January 17, 2000
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03L7/093; H03L7/07; H03L7/08; H03L7/089; H03L7/095
Domestic Patent References:
| JP9289447A | ||||
| JP1215122A | ||||
| JP63211819A |
Attorney, Agent or Firm:
Akira Matsumoto