Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP4095751
Kind Code:
B2
Abstract:
There is provided a semiconductor memory device capable of preventing the deterioration of access characteristics between output signal lines. The semiconductor memory device comprises: first and second cell arrays, each of which has the same number of memory cells; first through (2n-1)-th (n>=1) output selection control circuits; first through (2n-1)-th output transistor circuits which are provided so as to correspond to the first through (2n-1)-th output selection control circuits, and each of which receives the output of a corresponding one of the output transistor circuits; and first through (4n-2)-th output signal lines, each of the first and second cell arrays being divided into k (k>=2) first through k-th section parts, each of which has 2n-1 first through (2n-1)-th output parts and at least one auxiliary input/output part, the i-th (i=1, . . . , n-1) output selection control part receiving the output of the (2i-1)-th input/output part of each of the first through k-th section parts of the first cell array via the (2i-1)-th output signal line and receiving the output of the 2i-th input/output part of each of the first through k-th section parts of the first cell array via the 2i-th output signal line, the n-th output selection control part receiving the output of the (2n-1)-th input/output part of each of the first through k-th section parts of the first cell array via the (2n-1)-th output signal line and receiving the output of the auxiliary input/output part of each of the section parts of the first cell array via the 2n-th output signal line, and the (n+i)-th (i=1, . . . , n-1) output control circuit receiving the output of the (2i-1)-th input/output part of each of the first through k-th section parts of the second cell array via the (2n+2i-1)-th output signal line and receiving the output of the 2i-th input/output part of each of the first through k-th section parts of the second cell array via the (2n+2i)-th output signal line.
Inventors:
Nakao Takao
Makoto Segawa
Makoto Segawa
Application Number:
JP2000089702A
Publication Date:
June 04, 2008
Filing Date:
March 28, 2000
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G11C11/41; G11C7/10; G11C11/417
Domestic Patent References:
| JP2000012790A |
Attorney, Agent or Firm:
Kazuo Sato
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto