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Title:
半導体モジュールの製造方法
Document Type and Number:
Japanese Patent JP4096992
Kind Code:
B2
Abstract:

To provide the method of manufacturing a semiconductor module having a temperature hierarchy connection in which the defect of a void is reduced and the connection reliability of a high temperature side connection portion is maintained even in the case where the soldering of a lead-free solder material is carried out in the air.

There is provided the method of manufacturing an electron device comprising an electron component, a first substrate on which the electron component is mounted, and a second substrate on which the first substrate is mounted. The method comprises the first step of connecting the electrode of the electron component and the electrode of the first substrate by reflowing first lead-free solder which has a metal ball whose melting point is higher than those of an Sn solder ball and the Sn solder at temperature equal to or more than 240°C and equal to or less than the heat-resistant temperature of the electron component and in which the metal ball is covered with an Ni layer and the Ni layer is covered with an Au layer, and the second step of connecting the first substrate on which the electron component is mounted and the second substrate by reflowing second lead-free solder at temperature lower than a reflow temperature in the first step.

COPYRIGHT: (C)2008,JPO&INPIT


Inventors:
Tasao Soga
Hidee Shimokawa
Tetsuya Nakatsuka
Mikio Negishi
Koichi Nakajima
Tsuneo Endo
Application Number:
JP2007078132A
Publication Date:
June 04, 2008
Filing Date:
March 26, 2007
Export Citation:
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Assignee:
株式会社日立製作所
International Classes:
H05K3/34; B23K1/00; B23K35/26; H01L21/60; H01L25/00
Domestic Patent References:
JP2001308268A
JP7106731A
JP10163270A
JP2000517092A
JP2001144127A
JP8107261A
Attorney, Agent or Firm:
Manabu Inoue