Title:
消費電力特性計算手段及びその方法
Document Type and Number:
Japanese Patent JP4108805
Kind Code:
B2
Abstract:
A method for calculating a power consumption library on a gate level in a large-scale transistor circuit. The method includes: dividing a circuit network into a partial circuit network by a gate terminal of a transistor, calculating a relation of an input logical value to an output logical value in a partial circuit; calculating a relation of an output logical value to an input logical change in an output wiring between partial circuits, based on a partial circuit connection and a relation of an input logical value to an output logical value in a partial circuit; measuring a partial circuit power consumption by using an input logical change in each partial circuit; and regarding the sum of a power consumption at each partial circuit corresponding to an input logical change as a power consumption in a circuit network. The method also provides for reuse when a current path is the same in a circuit input logical change. The calculation also involves regarding the transistor as the same when a transistor with the same current characteristic is arrayed in the same order on the path even if a current path is different.
Inventors:
Kenji Shimazaki
Application Number:
JP946698A
Publication Date:
June 25, 2008
Filing Date:
January 21, 1998
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F17/50; H01L21/82
Domestic Patent References:
| JP9282346A |
Other References:
Wen-Zen Shen, at el,CB-Power: A Hierarchical Cell-Based Power Characterization and Estimation Environment for Static CMOS Circuits, Design Automation Conference 1997. Proceedings of the ASP-DAC '97,米国,IEEE,1997年 1月28日,p.189-194
Attorney, Agent or Firm:
Omae Kaname
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