Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP4115779
Kind Code:
B2
Abstract:
There a provided a first insulating layer formed over a semiconductor substrate, a cell plate line formed on the first insulating layer and having a slit that divides a region except a contact area into both sides, a capacitor dielectric layer formed on the cell plate on both sides of the slit and having a clearance over the slit, and a plurality of capacitor upper electrodes formed on the capacitor dielectric layer in one column on both sides of the slit.
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Inventors:
Genichi Komuro
Application Number:
JP2002256143A
Publication Date:
July 09, 2008
Filing Date:
August 30, 2002
Export Citation:
Assignee:
富士通株式会社
International Classes:
H01L21/8246; H01L27/105; H01L21/822; H01L21/8242; H01L27/04; H01L27/10; H01L27/108; H01L27/115; H01L29/04; H01L21/02
Domestic Patent References:
| JP2002094021A | ||||
| JP10229168A | ||||
| JP9289297A | ||||
| JP11068041A | ||||
| JP8335673A | ||||
| JP4049655A | ||||
| JP4340765A |
Attorney, Agent or Firm:
Keizo Okamoto