Title:
多層回路基板の形成方法および多層回路基板
Document Type and Number:
Japanese Patent JP4125644
Kind Code:
B2
Abstract:
A multilayered circuit board and a method of forming the multilayered circuit board are provided. In a first circuit forming process, a first circuit is formed on an insulating board with a conductor; in a circuit embedding process, the first circuit is embedded in the insulating board so as to have a predetermined surface flatness and a predetermined parallelism; in a masking process, a pilot hole for a via hole is masked at a part of a surface of the circuit; in an insulating layer forming process P 5 p, an insulating material is applied as a layer to the surface except that portion thereof covered by the mask; in an insulating material layer flattening process, the surface of the insulating material layer is flattened so as to have the predetermined surface flatness and the predetermined parallelism; and in a pilot hole forming process, the mask is removed.
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Inventors:
Kazuhiro Nishikawa
Tsukahara corporation
Hiroyuki Otani
Tsukahara corporation
Hiroyuki Otani
Application Number:
JP2003188290A
Publication Date:
July 30, 2008
Filing Date:
June 30, 2003
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H05K3/46; H05K3/00
Domestic Patent References:
| JP2001237542A | ||||
| JP6061627A | ||||
| JP7202429A | ||||
| JP11289163A | ||||
| JP5037128A | ||||
| JP10093233A | ||||
| JP2000236166A | ||||
| JP2001332866A | ||||
| JP63165877U | ||||
| JP2237195A | ||||
| JP2000349437A | ||||
| JP2001044590A |
Attorney, Agent or Firm:
Shiro Ogasawara
Previous Patent: JPH04125643
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