Title:
分布型増幅器
Document Type and Number:
Japanese Patent JP4154910
Kind Code:
B2
Abstract:
A distributed amplifier having a plurality of cascode amplifying circuits, and which causes little deterioration of the output waveform. In a preferred embodiment, the source potentials of the source-grounded transistors of the respective amplifying circuits are set individually. The source potentials of none or one or more of the source-grounded transistors are set at +0.8 volts, and the source potentials of the remaining source-grounded transistors are set at zero volts. The voltage gain of the source-grounded transistors whose source potential is +0.8 volts is zero, so that these source-grounded transistors do not contribute to the voltage gain of the amplifier as a whole. The source-grounded transistors whose source potential is zero volts contribute to the voltage gain, and output an amplified signal with a good waveform. The magnitude of the voltage gain can be adjusted by setting the number of source-grounded transistors whose source potential is zero volts.
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Inventors:
Yasunori Ogawa
Application Number:
JP2002094316A
Publication Date:
September 24, 2008
Filing Date:
March 29, 2002
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
H03F3/60; H03F1/22; H03F3/68
Domestic Patent References:
| JP11195939A | ||||
| JP10079629A | ||||
| JP2000349574A | ||||
| JP8111614A | ||||
| JP11195935A | ||||
| JP2001068952A |
Other References:
雨宮好文,現代電子回路学〔1〕,日本,株式会社オーム社,1987年 7月30日,第1版第17刷,p131-132、p134、p264
Attorney, Agent or Firm:
Takashi Ogaki