Title:
プログラマブル論理装置
Document Type and Number:
Japanese Patent JP4160956
Kind Code:
B2
Abstract:
The logic device (7) has a number of logic blocks (3A-3D) with configurable characteristics, each having at least one processing unit with function programs and interfaces for connection with each other logic block, at least one of the logic blocks having an input/output unit. The configuration of the logic device is determined by a configurable switching logic block (8) provided in a different plane (E2) to the plane (E1) containing the logic blocks.
Inventors:
Zeemers, Christian
Application Number:
JP2004547411A
Publication Date:
October 08, 2008
Filing Date:
October 23, 2003
Export Citation:
Assignee:
Siemens Aktiengesellschaft
International Classes:
H03K19/173; H03K19/177
Domestic Patent References:
| JP3132212A | ||||
| JP2002544699A | ||||
| JP11167556A | ||||
| JP11260928A |
Other References:
V.SKLYAROV,「Reconfigurable models of finite state machines and their implementation in FPGAs」,JOURNAL OF SYSTEMS ARCHITECTURE,NL,ELSEVIER SCIENCE PUBLISHERS BV.,2002年 8月,Vol.47、No.14-15,pp1043-1064,有限状態機械、FPGA
Attorney, Agent or Firm:
Iwao Yamaguchi
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