Title:
マイクロプロセッサ
Document Type and Number:
Japanese Patent JP4162825
Kind Code:
B2
Abstract:
A microprocessor includes an MMU which converts from a virtual address to a physical address, and an LSU which controls an execution of a load/store instruction. The LSU includes a DCACHE which temporarily stores data to read out from and to write into an external memory, an SPRAM used for a specific purpose besides caching, and an address generator which generates the virtual address to access the DCACHE and the SPRAM. The MMU generates a conversion table which performs a conversion from the virtual address to the physical address. A flag information showing whether or not the access to the SPRAM is performed is included in this conversion table. The LSU absolutely accesses the SPRAM if the flag is being set. Accordingly, it is unnecessary to allocate the SPRAM to a memory map of the main memory, and the allocation of the memory map simplifies.
Inventors:
Masashi Sasahara
Kam Ran, Malik
Rakish, agrawal
Michael lahm
Kam Ran, Malik
Rakish, agrawal
Michael lahm
Application Number:
JP2000029153A
Publication Date:
October 08, 2008
Filing Date:
February 07, 2000
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F12/08; G06F15/78; G06F12/10; G06F13/28
Domestic Patent References:
| JP10187533A | ||||
| JP4504626A |
Foreign References:
| WO1996036919A1 |
Attorney, Agent or Firm:
Kazuo Sato
Hidetoshi Tachibana
Yasukazu Sato
Yasushi Kawasaki
Hidetoshi Tachibana
Yasukazu Sato
Yasushi Kawasaki