Title:
システムレベルのシミュレーションにおけるスケジューリングの階層仕様方法
Document Type and Number:
Japanese Patent JP4177099
Kind Code:
B2
Abstract:
A method for hierarchical specification and modeling of scheduling in system-level simulations. The invention addresses the specification aspect by introducing an explicit notion of a scheduler that must be designed as part of the system. A scheduler effectively represents a scheduling policy for an architectural resource. A scheduling policy governs how behaviors assigned to a resource, gain access and share the resource. The invention includes a general framework for modeling a scheduling policy, which includes a simple mechanism that covers many common cases. This framework is part of a Virtual Component Codesign (VCC) process, which is targeted at consumer embedded system design. Two orthogonal models, one of a scheduler and one of a schedulable, comprise the overall modeling of scheduling in the invention. The two models interact by sending messages to each other via a simple protocol. The protocol itself is implemented by a pair of abstract interfaces, which in turn are implemented in concrete schedulable and scheduler objects in the simulator.
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Inventors:
Hoover, Christopher
Application Number:
JP2002536656A
Publication Date:
November 05, 2008
Filing Date:
October 17, 2001
Export Citation:
Assignee:
Cadence Design Systems, Inc.
International Classes:
G06F17/50; G06F9/44; G06F9/46
Foreign References:
| EP1022654A1 |
Other References:
Passerone, C. et al.,Trade-off evaluation in embedded system design via co-simulation,Proceedings of the ASP-DAC '97. Asia and South Pacific Design Automation Conference 1997,IEEE,1997年 1月28日,pp.291-297
Attorney, Agent or Firm:
Sadao Kumakura
Fumiaki Otsuka
Takaki Nishijima
Hiroyuki Suda
Hiroshi Uesugi
Fumiaki Otsuka
Takaki Nishijima
Hiroyuki Suda
Hiroshi Uesugi