Title:
電子部品の実装方法および実装構造体の製造方法
Document Type and Number:
Japanese Patent JP4181759
Kind Code:
B2
Abstract:
An electronic component that is provided with leads at a narrow pitch that are plated with solder is packaged by soldering the leads to lands (14) on a printed circuit board on which the lands (14) have been formed in a pattern of arrangement that corresponds to said leads. When packaging, solder paste (11) is printed over areas on the lands (14) that are greater in area than the area of the lands (14). The leads are then placed on this solder paste (11), and the solder paste (11) is subjected to reflow to solder the leads onto the lands (14).
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Inventors:
Hiroshi Sakai
Suzuki Motoharu
Makoto Igarashi
Akihiro Tanaka
Suzuki Motoharu
Makoto Igarashi
Akihiro Tanaka
Application Number:
JP2001167023A
Publication Date:
November 19, 2008
Filing Date:
June 01, 2001
Export Citation:
Assignee:
NEC
International Classes:
H05K3/34
Other References:
特開昭62-299098号公報
特開平6-169153号公報
特開平9-266373号公報
特開平6-169153号公報
特開平9-266373号公報
Attorney, Agent or Firm:
Masahiko Desk
Akitaka Kimura
Yasuhisa Tanizawa
Akitaka Kimura
Yasuhisa Tanizawa