Title:
同期式半導体記憶装置、及びその入力情報のラッチ制御方法
Document Type and Number:
Japanese Patent JP4190140
Kind Code:
B2
Abstract:
A synchronous semiconductor memory apparatus is capable of activating an input buffer circuit only in a required operating cycle and achieving low current consumption without degrading high speed response properties of an input buffer. When combination of control signals (Control) such as /CS, /RAS, /CAS, /WE and the like is directed to active command (ACTV), read command (READ, READA), write command (WRITE, WRITEA), mode register command (MRS), pre-charge command (PRE) and the like, a latch operation is dynamically performed for input from address pins. In this way, in the case where a signal iRAS is set at a low level, a latch signal aCLK is output to the rising edge of a signal iCLK, thereby latching addresses Add or the like. Alternatively, in the case where a signal iRAS or iCAS is set at a low level, the latch signal aCLK is output to the rising edge of the signal iCLK, thereby latching addresses Add or the like.
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Inventors:
Mitsuhiro Toho
Ito Shigema
Ito Shigema
Application Number:
JP2000266889A
Publication Date:
December 03, 2008
Filing Date:
September 04, 2000
Export Citation:
Assignee:
Fujitsu Microelectronics Limited
International Classes:
G11C11/407; G11C7/10; G11C8/06; G11C11/4076; G11C11/409; G11C11/4093; G11C16/02; G11C16/06
Domestic Patent References:
| JP9027192A | ||||
| JP11176164A | ||||
| JP11016346A | ||||
| JP2000163967A | ||||
| JP2000156082A | ||||
| JP2000048557A | ||||
| JP2000163965A | ||||
| JP2000132966A | ||||
| JP2000215664A | ||||
| JP2000513478A | ||||
| JP11031386A | ||||
| JP7230688A |
Attorney, Agent or Firm:
Hiroto Tanaka