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Title:
半導体集積回路装置
Document Type and Number:
Japanese Patent JP4205732
Kind Code:
B2
Abstract:
Semiconductor integrated circuit device wherein action for averting antenna effect has been taken, and method for producing a semiconductor integrated circuit device in which action for averting the antenna effect can be taken with ease. The method for producing a semiconductor integrated circuit device includes forming step of forming a semiconductor region of first conductivity type, a first diffusion region of the first conductivity type, formed in the semiconductor region of the first conductivity type, a gate insulating film formed in the semiconductor region of the first conductivity type, gate electrode on the gate insulating film and a wiring layer electrically connected to the gate electrode. The method also includes an investigating step of investigating, following the forming step, into whether or not it is necessary to take an action for averting an antenna effect in the wiring layer. The method also includes an action-taking step of replacing the first diffusion region of the first conductivity type by a second diffusion region of a second conductivity type, in case it is verified in the investigating step that it is necessary to take an action against the antenna effect. The second diffusion region of the second conductivity type forms a pn junction with the semiconductor region of the first conductivity type. The action-taking step also electrically connects the second region of the second conductivity type to the wiring layer.

Inventors:
Shuichi Nagase
Application Number:
JP2006133878A
Publication Date:
January 07, 2009
Filing Date:
May 12, 2006
Export Citation:
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Assignee:
Elpida Memory Co., Ltd.
International Classes:
H01L27/06; H01L21/822; H01L21/8234; H01L21/8238; H01L27/04; H01L27/088; H01L27/092
Domestic Patent References:
JP6125082A
JP2005259842A
JP2002100739A
JP2005294581A
JP6326248A
JP2000323582A
JP2001094060A
Attorney, Agent or Firm:
Kato Asamichi