Title:
半導体装置の設計方法および半導体装置の設計プログラム
Document Type and Number:
Japanese Patent JP4237133
Kind Code:
B2
Abstract:
It is an object of the present invention to provide a semiconductor device design method and program that can rapidly improve power supply noise characteristics and reduce the noise sufficiently without being restricted in design and noise solution. A step of performing frequency analysis on a power supply distribution network model creates a power supply distribution network model based on electric characteristics obtained in accordance with specifications (maximum allowable drop value of power supply voltage, power supply current value, operating frequency, etc.) of the semiconductor device and performs frequency analysis on this power supply distribution network model. A step of performing frequency analysis based on an operating current waveform analyzes power supply current characteristics based on an operating current waveform obtained in accordance with the specification. A step of calculating power supply noise calculates the power supply noise in accordance with analysis results of the step of performing frequency analysis on the power supply distribution network model and the step of performing frequency analysis based on the operating current waveform. It is thus possible to estimate the power supply noise before designing a circuit of the semiconductor device.
Inventors:
Kazuki Ogawa
Application Number:
JP2004349852A
Publication Date:
March 11, 2009
Filing Date:
December 02, 2004
Export Citation:
Assignee:
Fujitsu Microelectronics Limited
International Classes:
G06F17/50
Domestic Patent References:
JP2002222230A |
Attorney, Agent or Firm:
Hiroto Tanaka
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