Title:
非揮発性メモリ素子のNOR型メモリセルの製造方法
Document Type and Number:
Japanese Patent JP4245793
Kind Code:
B2
Abstract:
A method for fabricating NOR type memory cells of a nonvolatile memory device, floating gate insulating film, a floating gate electrode, a control gate insulating film, a control gate electrode, and an insulating film sequentially stacked in the shape of pattern on each of memory cell regions of a semiconductor substrate defined by an isolation film are formed; a source electrode and a drain electrode are formed in portions of the semiconductor substrate exposed at both sides of the gate electrode, a first etching barrier film is formed on the resultant; a first interlayer insulating film is formed on the first etching barrier film in a planarized fashion; a desired portion of the first interlayer insulating film is etched to form a first contact hole exposing the source and drain electrodes; a first conductive film in a planarized fashion is formed on the resultant to bury the first contact hole; the first conductive film is etched to form a source electrode line contacting the source electrode and a contact plug contacting the drain electrode; a second etching barrier film is formed on the resultant; a second interlayer insulating film is formed in a planarized fashion on the second etching barrier film; a desired portion of the second insulating film is etched to form second contact hole exposing the contact plug; and a bit line connected to the contact plug is formed via the second contact hole on the second interlayer insulating film.
Inventors:
Gold
Application Number:
JP2000309197A
Publication Date:
April 02, 2009
Filing Date:
October 10, 2000
Export Citation:
Assignee:
Tobu Electronics Co., Ltd.
International Classes:
H01L21/8247; H01L21/768; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP11017156A | ||||
| JP9064204A |
Attorney, Agent or Firm:
Shuichiro Kitamura