不揮発性半導体記憶装置 - 株式会社ルネサステクノロジ

Title:

不揮発性半導体記憶装置

Document Type and Number:

Japanese Patent JP4257214

Kind Code:

B2

Abstract:

A flash memory 1 based on the multilevel storage technology for storing the information of two or more bits is provided with four banks 2a to 2d. For example, in the left side of the bank 2a, a data latch 6a is provided along one short side of the bank 2a, while in the right side thereof, a data latch 6b is provided along the other short side of the bank 2a. At the lower side of the data latches 6a, 6b, arithmetic circuits 7a, 7b are provided. The data latches 6a, 6b are respectively formed of SRAMs. A sense latch 5a is divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latch 5a is connected with the data latches 6a, 6b via the signal lines respectively allocated along both short sides of the bank 2a.

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Inventors:

中島務
吉田敬一

Application Number:

JP2003572036A

Publication Date:

April 22, 2009

Filing Date:

February 28, 2002

Export Citation:

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Assignee:

株式会社ルネサステクノロジ

International Classes:

H01L27/10; G11C11/56; G11C16/02; G11C16/06; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; G11C16/26

Attorney, Agent or Firm:

筒井大和

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