Title:
プログラム可能時間遅延装置
Document Type and Number:
Japanese Patent JP4279888
Kind Code:
B2
Abstract:
Programmable time delay apparatus includes a plurality of similar components (10) which determine the total time delay of the apparatus. These components have gate units (310-31n, 320-32n, 330-33n, 340-34n) coupled thereto which, in response to a control signal (b0-bn) applied to each component, either electrically couples the component to the apparatus or electrically removes of the component from the apparatus. In a first embodiment, the control signals (b0-bn) place time delay components (10) in a series configuration, the total time delay being the sum of the time delays of each series-coupled component (10). In the second and third embodiment, the resistors (470-47n) and the capacitors (530-53n), respectively, are coupled in a capacitance charging circuit (470-47n, 43; 52, 530-53n), the coupled elements controlling the charging rate and, consequently, the time delay of the apparatus. By coupling the apparatus in a ring configuration (Fig. 6), a counter unit (63), counting the number of signal delays through the delay apparatus (61) can lengthen the programmed time delay.
Inventors:
Danny Earl Klein
Quong Hwahi
Quong Hwahi
Application Number:
JP2007101792A
Publication Date:
June 17, 2009
Filing Date:
April 09, 2007
Export Citation:
Assignee:
Texas Instruments Incorporated
International Classes:
G11C11/407; H03K5/13; G11C7/22; G11C8/18; G11C11/4076; H03K19/173
Domestic Patent References:
| JP5268015A | ||||
| JP410807A | ||||
| JP62207025A |
Foreign References:
| US4103251 |
Attorney, Agent or Firm:
Hideto Asamura
Hajime Asamura
Hayashi Zouzo
Kuniaki Shimizu
Hajime Asamura
Hayashi Zouzo
Kuniaki Shimizu