Title:
出力回路
Document Type and Number:
Japanese Patent JP4281193
Kind Code:
B2
Abstract:
A transistor output circuit featuring a low power consumption, high speed and stabilized operation is realized. The transistor output circuit of the invention is comprised of: transistors Q59 and Q57 having respective bases supplied with input signals in opposite phases, and respective emitters connected together; a transistor Q66 the base of which is connected to the collector of the transistor Q59; a diode Q65 connected to the emitter of the transistor Q66; a transistor Q63 the base of which is connected to the collector of transistor Q57 and to the other end of the diode Q65; resistances R73 and R74 connected to the emitter of the transistor Q63; a constant current supply Q64 connected to the resistances R73 and R74, provided with a bias circuit for setting its current at discretion; and transistor Q67 the base of which is, connected to a common connection point between the resistance and Q64, and the collector of which is connected to the emitter of transistor Q66: wherein this connection point between Q66 and Q67 is an output terminal.
Inventors:
Norio Koji
Hideyuki Nishioka
Hideyuki Nishioka
Application Number:
JP2000014805A
Publication Date:
June 17, 2009
Filing Date:
January 24, 2000
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H03K19/086; H03K19/00; H03K19/0175; H03K19/018
Domestic Patent References:
| JP5259887A | ||||
| JP5183418A | ||||
| JP8037456A | ||||
| JP9307424A | ||||
| JP2071611A |
Attorney, Agent or Firm:
Chieko Tateno