Title:
分散型多重化バス相互接続を最適化する方法と装置
Document Type and Number:
Japanese Patent JP4287368
Kind Code:
B2
Abstract:
Methods and apparatuses for optimizing distributed multiplexed bus interconnects are described. Parameters of components that make up a distributed multiplexed bus interconnect may be optimized, such as an amount of area on a chip occupied by the component, an amount of power consumed by the component, etc., while satisfying existing timing constraints between nodes of a distributed multiplexed bus interconnect.
Inventors:
Mayer, Michael Jay
Scott Shii, Evans
Cyneck, kamil
Scott Shii, Evans
Cyneck, kamil
Application Number:
JP2004506220A
Publication Date:
July 01, 2009
Filing Date:
May 14, 2003
Export Citation:
Assignee:
Sonics Incorporated
International Classes:
G06F17/50; H01L21/82
Domestic Patent References:
| JP9034927A | ||||
| JP2005539408A |
Foreign References:
| WO2000019343A1 |
Other References:
Pierre Guerrier, et al.,A Generic Architecture for On-Chip Packet-Switched Interconnections,Design, Automation, and Test in Europe,ACM,2000年,pp.250-256
Attorney, Agent or Firm:
Masaki Yamakawa
Shigeki Yamakawa
Shigeki Yamakawa
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