Title:
半導体ウェーハの研摩方法および装置
Document Type and Number:
Japanese Patent JP4334642
Kind Code:
B2
Abstract:
A system and method for planarizing a plurality of semiconductor wafers is provided. The method includes the steps of processing each wafer along the same process path using at least two polishing stations to each partially planarize the wafers. The system includes an improved process path exchanging a detachable wafer carrying head with spindles at each processing point and conveying the detached wafer carrying heads in a rotary index table between processing points. The system also provides for improved polishing accuracy using linear polishers having pneumatically adjustable belt tensioning and aligning capabilities.
Inventors:
Eric H Engdal
Edward Tee Fairy Jr.
Wilbur Sea Cruiser
La Fool Gyrus
Landar El Green
Annealed punt
Edward Tee Fairy Jr.
Wilbur Sea Cruiser
La Fool Gyrus
Landar El Green
Annealed punt
Application Number:
JP32239498A
Publication Date:
September 30, 2009
Filing Date:
November 12, 1998
Export Citation:
Assignee:
Rum Research Corporation
International Classes:
B24B37/00; B24B21/04; B24B21/10; B24B37/04; B24B37/27; B24B41/00; H01L21/304; H01L21/306; H01L21/3105
Domestic Patent References:
| JP9277165A | ||||
| JP8012469A | ||||
| JP58034751A | ||||
| JP62162466A | ||||
| JP9117857A | ||||
| JP2040917A | ||||
| JP61252069A | ||||
| JP4363032A | ||||
| JP1169027U | ||||
| JP9254018A | ||||
| JP2015257U |
Attorney, Agent or Firm:
Minoru Nakamura
Fumiaki Otsuka
Shishido Kaichi
Hideto Takeuchi
Toshio Imajo
Nobuo Ogawa
Village shrine Atsuo
Fumiaki Otsuka
Shishido Kaichi
Hideto Takeuchi
Toshio Imajo
Nobuo Ogawa
Village shrine Atsuo