Title:
メモリ装置及びメモリ制御方法
Document Type and Number:
Japanese Patent JP4356686
Kind Code:
B2
Abstract:
A memory control method is disclosed which includes: a storing step of storing a logical to physical conversion table retaining relations of correspondence between addresses of logical blocks in a user data area on the one hand, and addresses of physical blocks assigned to the logical blocks on the other hand, along with addresses of physical blocks in a cache area, the physical block addresses corresponding to the physical block addresses in the logical to physical conversion table; a first writing step of writing, to a deleted new cache block in the cache area, data in excess of a designated logical boundary which defines a logical space size in units of a plurality of sectors within a user data block of the user data area; and a second writing step of writing the data starting from the beginning of the new cache block upon data write in the first writing step to the new cache block, regardless of the logical address space of the new cache block.
Inventors:
Nobuhiro Kaneko
Kenichi Nakanishi
Kenichi Nakanishi
Application Number:
JP2005348111A
Publication Date:
November 04, 2009
Filing Date:
December 01, 2005
Export Citation:
Assignee:
ソニー株式会社
International Classes:
G06F12/16
Domestic Patent References:
| JP2003316659A | ||||
| JP11126488A | ||||
| JP11249968A | ||||
| JP2003015928A | ||||
| JP2005174468A | ||||
| JP9097206A | ||||
| JP2002091707A |
Foreign References:
| WO2002054247A1 |
Attorney, Agent or Firm:
Yoshitsuno Kakuda
Hitoshi Ito
Hitoshi Ito