Title:
マルチポートパケットプロセッサ
Document Type and Number:
Japanese Patent JP4368527
Kind Code:
B2
Abstract:
A multi-port packet processor on an integrated circuit provides an efficient means to interface multiple high-speed packet-based communications channels. The multi-port packet processor includes multiple port processors. Each port processor can include a channel interface for coupling to a respective communications channel, a channel processor for processing the data packets received through the channel interface, and an interprocessor communications interface for providing communication between the port processors. The channel interface can be designed to process data packets using a particular set of packet-based protocols. Alternatively, the channel interface can be designed having programmable controls to allow processing of data packets using a selected set, from a number of possible sets, of packet-based protocols.
Inventors:
Jennings Are W The Third
Application Number:
JP2000569552A
Publication Date:
November 18, 2009
Filing Date:
August 11, 1999
Export Citation:
Assignee:
MAGNACHIP SEMICONDUCTOR LTD
International Classes:
G06F15/163; H04L12/56; H04L12/44; H04L12/46; H04L12/66; H04L29/06
Domestic Patent References:
| JP11510012A | ||||
| JP10200567A | ||||
| JP5570053A | ||||
| JP6510635A |
Foreign References:
| WO1997004397A1 |
Attorney, Agent or Firm:
Minoru Nakamura
Fumiaki Otsuka
Sadao Kumakura
Shishido Kaichi
Nobuo Ogawa
Takaki Nishijima
Atsushi Hakoda
Hiroji Nakagawa
Fumiaki Otsuka
Sadao Kumakura
Shishido Kaichi
Nobuo Ogawa
Takaki Nishijima
Atsushi Hakoda
Hiroji Nakagawa