Title:
プラズマ処理室におけるウェハバイアス補償方法及び装置
Document Type and Number:
Japanese Patent JP4408569
Kind Code:
B2
Abstract:
Disclosed is a method and device for compensating a bias voltage on a wafer disposed over an electrostatic chuck in a processing chamber of a plasma processing system. The plasma processing system includes an electrostatic and RF power supplies that are coupled to the electrostatic chuck. The bias compensation device includes a voltage converter, a storage unit, and a voltage adjusting circuitry. The voltage converter is coupled to the electrostatic chuck for detecting a voltage Vpp of the electrostatic chuck. The voltage converter converts the detected voltage to a lower voltage Vref. The storage unit stores a predetermined slope and a predetermined offset of a calibration curve, which is derived by fitting a plurality of wafer bias voltages as a function of electrostatic chuck voltages.
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Inventors:
Shoep Alan M.
Nop Robert E.
Olson Christopher H.
Barnes Michael S.
Ngo Tuan M.
Nop Robert E.
Olson Christopher H.
Barnes Michael S.
Ngo Tuan M.
Application Number:
JP2000575158A
Publication Date:
February 03, 2010
Filing Date:
October 05, 1999
Export Citation:
Assignee:
LAM RESEARCH CORPORATION
International Classes:
H01L21/302; H01L21/3065; H01L21/683; H02N13/00
Domestic Patent References:
| JP2000049216A | ||||
| JP9120957A | ||||
| JP7074160A | ||||
| JP62193126A | ||||
| JP6326176A |
Attorney, Agent or Firm:
Meisei International Patent Office