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Title:
半導体装置の設計システム及びコスト評価方法
Document Type and Number:
Japanese Patent JP4409363
Kind Code:
B2
Abstract:

To provide a design system for a semiconductor device which permits the evaluation of finally expected cost at the initial stage of the design of a three-dimensional mounting circuit.

The design system is provided with an arrangement connection information storage means 2 for storing arrangement data, die shape data, terminal data and connection data of each die, a wiring rule storage means 7, a cost calculating formula storage means 10 for storing a cost calculating formula by cost calculation parameters including the height of a stacked die, a step count, a plane view area and a necessary substrate area, a three-dimensional information calculation means 3 for calculating the height of the die, a lamination layer stage count and a plane view area, a wiring terminal coordinate calculating means 5, a virtual wiring means 8 which performs virtual wiring among respective wiring terminals designated by the connection data and calculates a substrate area necessary for the virtual wiring, and a cost calculating means 11 which uses the cost calculation parameters to calculate cost by the cost calculating formula.

COPYRIGHT: (C)2006,JPO&NCIPI


Inventors:
Tomokei Hajime
Cui cloud
Kawase English Road
Minako Mikami
Fumiaki Shigeoka
Hiroyuki Kataoka
Seiichiro Yoshida
Naoto Ishibashi
Matsuoka Tsunehiro
Otsuru Eisa Saku
Yoichi Ieri
Application Number:
JP2004161062A
Publication Date:
February 03, 2010
Filing Date:
May 31, 2004
Export Citation:
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Assignee:
Fukuoka Prefecture Industrial and Science Promotion Foundation
Ueno Seiki Co., Ltd.
Gedat Innovation Co., Ltd.
New Japan Radio Co., Ltd.
International Classes:
G06F17/50; H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
JP2003203094A
JP2002171099A
JP2002169839A
Attorney, Agent or Firm:
Kazuto Ishida