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Title:
半導体集積回路の同時スイッチング出力ノイズ見積もり方法及び装置並びに半導体集積回路の設計方法及び装置
Document Type and Number:
Japanese Patent JP4432606
Kind Code:
B2
Abstract:

To provide a method for estimating SSO noise capable of estimating the SSO (simultaneous switching output) noise of a semiconductor integrated circuit by analytical calculation in a short time without performing circuit simulation.

The method and device for estimating the SSO noise of the semiconductor integrated circuit, A SSO noise calculation means 27 calculates based on electrical-characteristics information on a package (inductance of a lead, inductance of a bonding wire) stored in a package electrical-characteristics information storage means 23, constitution information on an input/output circuit (kind and number of a signal circuit, a kind and number of a power supply circuit) stored in an input/output circuit configuration information storage means 24, the electrical-characteristics information on the package and a parameter for estimating the SSO noise stored in a parameter storage means 25 for estimating the SSO noise.

COPYRIGHT: (C)2005,JPO&NCIPI


Inventors:
Tetsutaro Hashimoto
Ryo Shibata
Kenji Wada
Takashi Kurihara
Application Number:
JP2004142130A
Publication Date:
March 17, 2010
Filing Date:
May 12, 2004
Export Citation:
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Assignee:
富士通株式会社
International Classes:
G06F17/50; H01L21/822; H01L27/04; H03K19/00
Domestic Patent References:
JP9305649A
JP8278992A
JP9097273A
JP2004318640A
JP2001236372A
Attorney, Agent or Firm:
Tetsuo Hirado



 
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