Title:
酸化誘起積層欠陥を実質的に有さない空孔優勢コアを有する低欠陥密度シリコン
Document Type and Number:
Japanese Patent JP4439810
Kind Code:
B2
Abstract:
The present invention relates to a process for preparing a single crystal silicon ingot, as well as to the ingot or wafer resulting therefrom. The process comprises controlling (I) a growth velocity, v, (ii) an average axial temperature gradient, G, and (iii) a cooling rate of the crystal from solidification to about 750 DEG C, in order to cause the formation of a segment having a first axially symmetric region extending radially inward from the lateral surface of the ingot wherein silicon self-interstitials are the predominant intrinsic point defect, and a second axially symmetric region extending radially inward from the first and toward the central axis of the ingot.; the process is characterised in that v, G and the cooling rate are controlled to prevent the formation of agglomerated intrinsic point defects in the first region, while the cooling rate is further controlled to limit the formation of oxidation induced stacking faults in a wafer derived from this segment, upon subjecting the wafer to an oxidation treatment otherwise suitable for the formation of such faults.
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Inventors:
Jang Bum Kim
Steven El Kimbell
Jeffrey El Revert
Mosen Banan
Steven El Kimbell
Jeffrey El Revert
Mosen Banan
Application Number:
JP2002559879A
Publication Date:
March 24, 2010
Filing Date:
January 22, 2002
Export Citation:
Assignee:
MEMC ELECTRONIC MATERIALS,INCORPORATED
International Classes:
C30B29/06; C30B15/00; C30B15/20; C30B33/02
Domestic Patent References:
| JP2000513696A | ||||
| JP11147786A | ||||
| JP2000264783A | ||||
| JP10326790A | ||||
| JP11092272A | ||||
| JP2000034192A | ||||
| JP6279169A |
Attorney, Agent or Firm:
Samejima Mutsumi
Kyousei Tamura
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Hiroshi Sato
Kyousei Tamura
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Hiroshi Sato