Title:
光導波路基板及びその製造方法
Document Type and Number:
Japanese Patent JP4440697
Kind Code:
B2
Abstract:
The present invention relates to an optical waveguide chip, etc., having a structure for effectively avoiding or suppressing peeling of an optical waveguide layer in a process of cutting a wafer. The optical waveguide chip comprises a substrate having a main surface, and an optical waveguide layer formed on the main surface of the substrate. The optical waveguide layer comprises a cladding portion and a core portion that is disposed inside the cladding portion and that has a higher refractive index than the cladding portion, and at least one of side surfaces of the optical waveguide layer is positioned at a predetermined distance toward a center of the main surface from an edge of the main surface. This arrangement includes an arrangement having a thin film portion at a peripheral region that includes the edge of the main surface. In the case that the optical waveguide layer has the thin film portion at its periphery, the optical waveguide layer has a side surface that coincide with the side surface of the substrate including the edge of the main surface and a side surface that is separated by a predetermined distance from edge of the main surface. By this arrangement, when cutting a wafer into chip units, even if chipping occurs at an edge of the main surface of the substrate to be cut, peeling of the optical waveguide layer, formed on the substrate, is suppressed effectively.
Inventors:
Takafumi Nono
Katsumi Shibayama
Katsumi Shibayama
Application Number:
JP2004127150A
Publication Date:
March 24, 2010
Filing Date:
April 22, 2004
Export Citation:
Assignee:
Hamamatsu Photonics Co., Ltd.
International Classes:
G02B6/122; G02B6/13; G02B6/30
Domestic Patent References:
| JP2002022993A | ||||
| JP8162718A |
Foreign References:
| WO1998013862A1 | ||||
| US20030194192 |
Attorney, Agent or Firm:
Yoshiki Hasegawa
Shiro Terasaki
Satoru Ishida
Shiro Terasaki
Satoru Ishida