Title:
半導体装置及びその製造方法
Document Type and Number:
Japanese Patent JP4455427
Kind Code:
B2
Abstract:
It is possible to provide a semiconductor device including a CMOS device having a gate electrode, in which the variation in threshold voltage is little. There are a p-channel MIS transistor and a n-channel MIS transistor which are provided in a semiconductor substrate, and in a region of a gate electrode of the p-channel MIS transistor at least 1 nm or less apart from the interface with a gate insulating film, the oxygen concentration is 1020 cm-3 or more and 1022 cm-3 or less.
Inventors:
Masato Koyama
Yoshinori Tsuchiya
Ichihara Reika
Yoshinori Tsuchiya
Ichihara Reika
Application Number:
JP2005190018A
Publication Date:
April 21, 2010
Filing Date:
June 29, 2005
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/8238; H01L21/336; H01L27/092; H01L29/423; H01L29/49; H01L29/78; H01L29/786
Domestic Patent References:
| JP2003273350A | ||||
| JP2005005603A | ||||
| JP2004186693A | ||||
| JP2000138373A | ||||
| JP2001358225A |
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki