Title:
シリサイド層の形成方法
Document Type and Number:
Japanese Patent JP4458685
Kind Code:
B2
Abstract:
A method of forming silicide, especially in a CMOS device in which polysilicon grains in a p-type gate are re-doped with n-type impurities such as As and the like at a critical implantation dose. This increases the grain size of the polysilicon, which also reduces sheet resistance by securing thermal stability in subsequent process steps thereof. The present invention generally includes forming an undoped polysilicon layer, doping the polysilicon layer with p-type impurity ions, doping the p-doped polysilicon layer with ions that increase the grain size of the polysilicon layer by being heated, forming a metal layer on the twice-doped polysilicon layer, and forming a silicide layer by reacting a portion of the twice-doped polysilicon layer with the metal layer.
Inventors:
Lee Ki Min
Security Gyun
Security Gyun
Application Number:
JP2001013292A
Publication Date:
April 28, 2010
Filing Date:
January 22, 2001
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
H01L21/24; H01L21/8238; H01L21/28; H01L27/092; H01L29/78
Domestic Patent References:
| JP11233646A | ||||
| JP1173713A | ||||
| JP6224380A | ||||
| JP62210664A | ||||
| JP11016855A | ||||
| JP11067690A |
Attorney, Agent or Firm:
Eiji Saegusa
Kakehi Yuro
Kimio Matsumoto
Kakehi Yuro
Kimio Matsumoto