リフレッシュカウンタ回路及びリフレッシュ動作の制御方法

Japanese Patent JP4470161

B2

A refresh counter circuit generating a row address during refresh operation for the memory device which has a normal area for storing data bits and a parity area for storing parity bits, including; n-stage counter which generates the row address corresponding to an address space of the normal area represented by n bits and the parity area represented by m (m