Title:
パリティ生成回路,パリティ生成回路用構成回路,情報処理装置,及びエンコーダ
Document Type and Number:
Japanese Patent JP4485577
Kind Code:
B2
Abstract:
In order to generate a parity of output data from a priority encoder without increasing processing time or making the circuitry complex, the present invention a first level generator (4) having a plurality of first component circuits (10-1 to 10-8) arranged in parallel, into each of which one of a plurality of sets of a specific number of bits of the binary data in sequence from the most significant bit is input and each of which generates and outputs a first signal for parity generation of bit data of the specific number of bits and a second signal representing whether or not the entire bit data of the specific number of bits is "0s" or "1s"; and a second level generator (5) generating the parity of the binary data based on the first signal and the second signal from each of said first component circuits (10-1 to 10-8) of said first level generator (4).
Inventors:
Moriyuki Yamato
Application Number:
JP2007556749A
Publication Date:
June 23, 2010
Filing Date:
February 01, 2006
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F7/38; G06F7/74; G06F11/10
Domestic Patent References:
| JP2000259392A | ||||
| JP8030436A |
Attorney, Agent or Firm:
Yu Sanada
Masahisa Yamamoto
Masahisa Yamamoto