Title:
不揮発性半導体記憶装置
Document Type and Number:
Japanese Patent JP4489359
Kind Code:
B2
Abstract:
A nonvolatile semiconductor memory device configured by a select MOS transistor provided with a gate insulator film and a select gate electrode, as well as a memory MOS transistor provided with a capacitor insulator film comprising a lower potential barrier film, a charge trapping film, and an upper potential barrier film, as well as a memory gate electrode. The charge trapping film is formed with a silicon oxynitride film and the upper potential barrier film is omitted or its thickness is limited to 1 nm and under to prevent the Gm degradation to be caused by the silicon oxynitride film, thereby lowering the erasure gate voltage. The charge trapping film is formed with a silicon oxynitride film used as a main charge trapping film and a silicon nitride film formed on or beneath the silicon oxynitride film so as to form a potential barrier effective only for holes. And, a hot-hole erasing method is employed to lower the erasure voltage.
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Inventors:
Toshiyuki Mine
Takashi Hashimoto
Western Izumiichi
Nozomi Matsuzaki
Hitoshi Kume
Jiro Yugami
Takashi Hashimoto
Western Izumiichi
Nozomi Matsuzaki
Hitoshi Kume
Jiro Yugami
Application Number:
JP2003023690A
Publication Date:
June 23, 2010
Filing Date:
January 31, 2003
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H01L21/8247; H01L21/28; H01L21/336; H01L27/115; H01L29/788; H01L29/792; G11C16/04
Domestic Patent References:
| JP2002164449A | ||||
| JP2001102466A | ||||
| JP2001358237A | ||||
| JP2002289708A | ||||
| JP2002261175A | ||||
| JP2002217317A |
Attorney, Agent or Firm:
Yamato Tsutsui