Title:
MISトランジスタを半導体基板上に製造する方法
Document Type and Number:
Japanese Patent JP4489968
Kind Code:
B2
Abstract:
The invention relates to an MIS transistor comprising a channel region (118), source (114) and drain (116) regions arranged on either side of the channel, and a gate (150) set closely above the channel region. According to the invention, the channel has a doped central part (140), located between the source and drain regions, and separated from said source and drain regions.
Inventors:
Druonibu, Simon
Gugan, Georges
Kaiya, Christian
Kudale, Fabian
Gugan, Georges
Kaiya, Christian
Kudale, Fabian
Application Number:
JP2000594148A
Publication Date:
June 23, 2010
Filing Date:
January 13, 2000
Export Citation:
Assignee:
COMPAGNIE GENERALE DES MATIERES NUCLEAIRES
International Classes:
H01L29/41; H01L29/78; H01L21/28; H01L21/336; H01L29/10; H01L29/423; H01L29/43; H01L29/49
Domestic Patent References:
| JP9321278A | ||||
| JP6204469A | ||||
| JP3268434A | ||||
| JP11251454A |
Attorney, Agent or Firm:
Hideto Asamura
Hajime Asamura
Katsunori Ando
Taro Akazawa
Hajime Asamura
Katsunori Ando
Taro Akazawa