Title:
パイプラッチ回路を有するメモリ素子
Document Type and Number:
Japanese Patent JP4500969
Kind Code:
B2
Abstract:
A memory device having a plurality of pipelatch circuits storing data from memory cells via global input/output lines, a pipelatch input control circuit to selectively couple the pipelatch circuit to the global input/output lines in response to a pipelatch control signal, and a pipe count signal generator to control a data path between the pipelatch circuits and an output driver, wherein the pipelatch input control circuit includes: a first control signal generator receiving a first control signal and global input/output line signals and producing a pass gate control signal; a second control signal generator receiving the first control signal and the pass gate control signal and producing a plurality of second control signals; a third control signal generator receiving the pass gate control signal and producing a third control signal by combining the pass gate control signal and a delay signal of the pass gate control signal; and a fourth control signal generator receiving the first control signal, the plurality of second control signals and the third control signal and producing the pipelatch control signal.
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Inventors:
Kim Hiko
Zheng Dong planting
Zheng Dong planting
Application Number:
JP2000193821A
Publication Date:
July 14, 2010
Filing Date:
June 28, 2000
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
G11C11/407; G11C7/10; G11C11/406; G11C11/4076; G11C11/4093; G11C11/4096
Domestic Patent References:
| JP10188556A | ||||
| JP11149776A | ||||
| JP8212778A | ||||
| JP9091955A | ||||
| JP9106671A |
Attorney, Agent or Firm:
Patent Business Corporation Saegusa International Patent Office