Title:
電子部品内蔵基板及びその製造方法
Document Type and Number:
Japanese Patent JP4518113
Kind Code:
B2
Abstract:
A method of manufacturing an electronic component-embedded board is provided which is capable of suppressing warpage without requiring complicated processes at low cost and which offers high productivity and economic efficiency. A worksheet 100 includes insulating layers 21 and 31 on one surface of an approximately rectangular substrate 11, and an electronic component 41 and a plate-like frame member (member) 51 embedded inside the insulating layer 21, wherein the plate-like frame member 51 satisfying the relationship represented by the following formula (1) :±1 <±3 and ±2 <±3 ... (1), is mounted on an unmounted portion of the electronic component 41 on the substrate 11. In the formula, ±1, ±2 and ±3 respectively denote the linear coefficients of thermal expansion (ppm/K) of the electronic component 41, the plate-like frame member 51, and the substrate 11, the respective wiring layers or the respective insulating layers.
Inventors:
Zenichi Kanamaru
Takaaki Morita
Kenichi Kawabata
Takaaki Morita
Kenichi Kawabata
Application Number:
JP2007193836A
Publication Date:
August 04, 2010
Filing Date:
July 25, 2007
Export Citation:
Assignee:
tdk Corporation
International Classes:
H05K3/46; H05K1/02
Domestic Patent References:
| JP2006261245A | ||||
| JP2004311598A | ||||
| JP200471698A | ||||
| JP200472032A | ||||
| JP200216173A | ||||
| JP2006261246A | ||||
| JP2005251792A |
Attorney, Agent or Firm:
Yoshiyuki Inaba
Shinji Oga
Toshifumi Onuki
Takuji Fukasawa
Shinji Oga
Toshifumi Onuki
Takuji Fukasawa