Title:
故障解析装置
Document Type and Number:
Japanese Patent JP4523659
Kind Code:
B2
Abstract:
Relating with board numbers of the boards mounted with the logic circuits and mounted places on the boards and in relation to log information to be collected from the logic circuits, analysis information describing information to be processed when the log information is generated, information of a condition for which the log information is to be valid, and information of a condition for which the log information is to be invalid are defined for analyzing failures using the analysis information based on the logic circuits. Upon the realization of the failure analysis based on the logic circuits, the analysis information further describes information of the priority of the log information to realize a thorough analysis of critical failures.
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Inventors:
Masato Nakagawa
Application Number:
JP2008502565A
Publication Date:
August 11, 2010
Filing Date:
February 27, 2006
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F11/22
Domestic Patent References:
| JP2001331350A | 2001-11-30 | |||
| JP2003162430A | 2003-06-06 | |||
| JP2005284357A | 2005-10-13 | |||
| JP2005004326A | 2005-01-06 | |||
| JPH10260861A | 1998-09-29 | |||
| JPH0520109A | 1993-01-29 |
Foreign References:
| WO2005091098A1 | 2005-09-29 |
Attorney, Agent or Firm:
Akihiko Watanabe
Keiko Shigehisa
Keiko Shigehisa