Title:
半導体装置
Document Type and Number:
Japanese Patent JP4555540
Kind Code:
B2
Abstract:
An interconnect trench is formed on a dielectric layer 12 and a first HSQ layer 14 formed on a semiconductor substrate, and a tantalum family barrier metal layer 24a is formed all over the substrate. Then a seed copper-containing metal layer 60 and a plated copper layer 62 are formed so as to fill a part of the interconnect trench. After that, a bias-sputtered copper-containing metal layer 64 is formed on the plated copper layer 62 so as to fill the remaining portion of the interconnect trench and then heat treatment is performed. As a result, a dissimilar metal contained in the bias-sputtered copper-containing metal layer 64 diffuses uniformly into the plated copper layer 62.
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Inventors:
Hiroyuki Kunishima
Toshiji Takewaki
Toshiji Takewaki
Application Number:
JP2002198432A
Publication Date:
October 06, 2010
Filing Date:
July 08, 2002
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/3205; H01L21/285; H01L21/288; H01L21/60; H01L21/768; H01L23/52; H01L23/532
Domestic Patent References:
| JP2000049229A | ||||
| JP2000306996A | ||||
| JP2000349085A | ||||
| JP11204524A | ||||
| JP6275617A |
Attorney, Agent or Firm:
Shinji Hayami
Kana Nomoto
Satoshi Amagi
Kana Nomoto
Satoshi Amagi