Title:
多層印刷回路を形成するための積層方法
Document Type and Number:
Japanese Patent JP4565606
Kind Code:
B2
Abstract:
A process for correctly positioning layers of a multilayer printed circuit. A flat closed circuit is attached peripherally on each layer. Each layer is arranged parallel to multiple circuits that are fixed on a reference board. An alternating current flows in one of the fixed circuits. The alternating current electromagnetically induces a current in the flat closed circuit, which in turn electromagnetically induces electromotive forces in other fixed circuits. The characteristic values of the electromotive forces are a function of the relative positions of the fixed circuits with respect to the flat, closed circuit. These values are used to correct the position of each layer on which the circuit is attached until each layer or parts of each layer are stacked in a predetermined position relative to at least parts of the fixed circuits. The corrected position is the position which each layer must maintain in the multilayer circuit. The layers are secured by hot soldering of interposed sheets of synthetic resin.
Inventors:
Amman, beat
Application Number:
JP2001576730A
Publication Date:
October 20, 2010
Filing Date:
February 07, 2001
Export Citation:
Assignee:
Ballado Investments Inc.
International Classes:
H05K3/46; H05K1/02
Domestic Patent References:
| JP3253095A | ||||
| JP61125715A |
Attorney, Agent or Firm:
Minoru Yoshida
Tatsuya Tanaka
Yoshikazu Fukumoto
Tsukasa Senba
Takashi Shiotani
Hiroshi Furusawa
Masato Tsutsui
Tatsuya Tanaka
Yoshikazu Fukumoto
Tsukasa Senba
Takashi Shiotani
Hiroshi Furusawa
Masato Tsutsui