Title:
TLBロックインジケータ
Document Type and Number:
Japanese Patent JP4567789
Kind Code:
B2
Abstract:
A processor includes a hierarchical Translation Lookaside Buffer (TLB) comprising a Level-1 TLB and a small, high-speed Level-0 TLB. Entries in the L0 TLB replicate entries in the L1 TLB. The processor first accesses the L0 TLB in an address translation, and access the L1 TLB if a virtual address misses in the L0 TLB. When the virtual address hits in the L1 TLB, the virtual address, physical address, and page attributes are written to the L0 TLB, replacing an existing entry if the L0 TLB is full. The entry may be locked against replacement in the L0 TLB in response to an L0 Lock (L0L) indicator in the L1 TLB entry. Similarly, in a hardware-managed L1 TLB, entries may be locked against replacement in response to an L1 Lock (L1L) indicator in the corresponding page table entry.
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Inventors:
Augsburg, Victor Roberts
Defender Fur, James Norris
Bridges, Jeffrey Todd
Sir Torius, Thomas Andrew
Defender Fur, James Norris
Bridges, Jeffrey Todd
Sir Torius, Thomas Andrew
Application Number:
JP2008528104A
Publication Date:
October 20, 2010
Filing Date:
August 22, 2006
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
G06F12/10; G06F12/12
Domestic Patent References:
| JP2002149490A | ||||
| JP62156744A | ||||
| JP2004334267A |
Foreign References:
| US4727485 |
Attorney, Agent or Firm:
Kurata Masatoshi
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Katsumura Hiro
Ryo Hashimoto
Tetsuya Kazama
Shoji Kawai
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takuzo Ichihara
Yamashita Gen
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Katsumura Hiro
Ryo Hashimoto
Tetsuya Kazama
Shoji Kawai
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takuzo Ichihara
Yamashita Gen