Title:
チップスケールパッケージ、はんだバンプ半導体ウェハ構造及び集積回路用のフリップチップパッケージの形成方法
Document Type and Number:
Japanese Patent JP4580550
Kind Code:
B2
Abstract:
A chip scale (8) package comprising in combination:
a. an integrated circuit (10) formed upon a semiconductor die, said semiconductor die having a front surface (12) and an opposing rear surface (16), said semiconductor die including a plurality of conductive bond pads (18, 20) formed upon the front surface thereof for making electrical interconnections to said integrated circuit;
b. a patterned metal layer (30) formed over the front surface (12) of said semiconductor die, said patterned metal layer providing a plurality of solder bump pads (26) upon the front surface of said semiconductor die, and said patterned metal layer electrically coupling said conductive bond pads to said plurality of solder bump pads;
c. a plurality of ductile solder balls (28), each of said ductile solder balls being secured to a corresponding one of said solder bump pads, each of said ductile solder balls having a generally spherical shape and measuring at least 9 mils (.009 inch) in diameter.
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Inventors:
Eleanus, Peter
Hollac, Harry
Hollac, Harry
Application Number:
JP2000517447A
Publication Date:
November 17, 2010
Filing Date:
October 19, 1998
Export Citation:
Assignee:
Flip Chip International LLC
International Classes:
H01L23/12; H01L23/52; G06F1/16; H01L21/3205; H01L21/60; H01L23/31
Domestic Patent References:
| JP8097217A | ||||
| JP9232464A | ||||
| JP6045740A | ||||
| JP8330313A | ||||
| JP9172036A | ||||
| JP8064725A | ||||
| JP8340002A | ||||
| JP8250498A | ||||
| JP61295639A |
Attorney, Agent or Firm:
Kenji Sugimura
Tatsuya Sawada
Harima Satoko
Takamatsu Kaoru
Tatsuya Sawada
Harima Satoko
Takamatsu Kaoru