Title:
SRAM素子及びその製造方法
Document Type and Number:
Japanese Patent JP4648296
Kind Code:
B2
Abstract:
Disclosed is a static random access memory (SRAM), which includes first and second access transistors composed of metal oxide semiconductor (MOS) transistors, first and second drive transistors composed of MOS transistors, and first and second p-channel thin film transistors (TFTs) used as pull-up devices. The SRAM includes a ground potential layer disposed as a common source of the first and second drive transistors, and formed by implanting a dopant into a semiconductor substrate, a power supply potential layer connected with sources of the first and second p-channel TFTs, and an insulating layer formed on the substrate and interposed between the ground potential layer and the power supply potential layer.
Inventors:
Park, Sun Hee
Application Number:
JP2006339792A
Publication Date:
March 09, 2011
Filing Date:
December 18, 2006
Export Citation:
Assignee:
Tobu Electronics Co., Ltd.
International Classes:
H01L27/11; H01L21/8244
Domestic Patent References:
| JP6502963A | ||||
| JP2172273A | ||||
| JP4061160A | ||||
| JP6112439A |
Attorney, Agent or Firm:
Masaki Yamakawa
Shigeki Yamakawa
Shigeki Yamakawa