Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP4665140
Kind Code:
B2
Abstract:
A first MISFET is formed in a first active region on the surface of a semiconductor substrate. The drain region of the first MISFET has a lightly doped drain structure with a low concentration region and a high concentration region. The side wall spacer conformingly covers the side wall of the gate electrode and the surface of the low concentration region in the drain region. A second MISFET is formed in a second active region. The side wall spacer of the second MISFET covers the side wall of the gate electrode and extends to the surface of the source and drain regions. An interlayer insulating film covers the said first MISFET and second MISFET and is made of material having an etching resistance different from that of the side wall spacers of the first MISFET and second MISFET.
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Inventors:
Hirofumi Wataya
Application Number:
JP2000278587A
Publication Date:
April 06, 2011
Filing Date:
September 13, 2000
Export Citation:
Assignee:
Fujitsu Semiconductor Limited
International Classes:
H01L27/088; H01L21/60; H01L21/8234; H01L21/8238; H01L21/8242; H01L27/092; H01L27/108; H01L21/02
Domestic Patent References:
| JP11186520A | ||||
| JP10242420A | ||||
| JP2000031088A | ||||
| JP11031799A |
Attorney, Agent or Firm:
Keishiro Takahashi
Mikio Kuruyama
Mikio Kuruyama