Title:
半導体素子の製造方法
Document Type and Number:
Japanese Patent JP4677177
Kind Code:
B2
Abstract:
A method for manufacturing a semiconductor device wherein a cylindrical capacitor is formed by selectively etching an oxide film in a cell area for preventing bridging between cells during a wet etching process of the oxide film in the cell area is described herein. A step difference between the interlayer insulating film formed in the cell area and the interlayer insulating film formed in the peripheral circuit area is minimized by covering the peripheral circuit area by the photoresist film and selectively etching the oxide film in the cell area to form a cylindrical capacitor, thereby simplifying the manufacturing process. In addition, bridging between the cells is prevented by performing a simple wet etching process using a single wet station, without performing a separate dry etching process for removing the oxide film and the photoresist film pattern, thereby improving the yield of the device.
Inventors:
Money
Youne Takane
Choi Satoshi
Youne Takane
Choi Satoshi
Application Number:
JP2003185463A
Publication Date:
April 27, 2011
Filing Date:
June 27, 2003
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
H01L21/308; H01L27/108; H01L21/304; H01L21/306; H01L21/311; H01L21/316; H01L21/8242
Domestic Patent References:
| JP2000196038A | ||||
| JP2001237400A | ||||
| JP11087281A | ||||
| JP8187475A | ||||
| JP7050281A | ||||
| JP2001308052A | ||||
| JP2001527697A | ||||
| JP6236971A | ||||
| JP2002184741A |
Attorney, Agent or Firm:
Hiroshi Arafune
Yoshio Arafune
Yoshio Arafune