Title:
デエンファシス機能を有する出力バッファ回路
Document Type and Number:
Japanese Patent JP4680004
Kind Code:
B2
Abstract:
Disclosed is an output buffer circuit including main-data output buffers; a de-emphasis output buffer; and a selector that performs switching control in such a way that, based on a control signal indicating whether de-emphasis is to be enabled or disabled, main data is supplied to the de-emphasis output buffer to make the buffer operate as a main-data output buffer when the control signal indicates that de-emphasis is to be disabled, while emphasis data obtained on delaying the main data by the delay circuit is supplied to the de-emphasis output buffer to make the buffer operate as a de-emphasis output buffer when the control signal indicates that de-emphasis is to be enabled.
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Inventors:
Makoto Tanaka
Application Number:
JP2005240775A
Publication Date:
May 11, 2011
Filing Date:
August 23, 2005
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H04L25/03; H03K19/0175; H04L25/02
Domestic Patent References:
| JP2002094365A | ||||
| JP2004228613A | ||||
| JP2004312614A | ||||
| JP2004336407A | ||||
| JP63204757A | ||||
| JP2125518A | ||||
| JP8220196A | ||||
| JP9101346A | ||||
| JP5129926A |
Attorney, Agent or Firm:
Kato Asamichi