Title:
画像復号装置及び方法
Document Type and Number:
Japanese Patent JP4680608
Kind Code:
B2
Abstract:
A picture decoding device (100) comprises a decoding unit (30), a frame memory (40), a deblocking filter (50), a macro block memory (60), and a control unit (70). The macro block memory (60) stores an unfiltered picture data, for which deblock-filtering is not performed, of the macro blocks adjoining a slice boundary. Decoding and deblock-filtering are performed for the macro blocks of each slice in a manner of pipeline processing, and the decoded picture data for the macro blocks is stored in the frame memory (40). After the pipeline processing for all of the macro blocks is completed, the second deblock-filtering is performed to the slice boundary-adjoining macro blocks, and the pixel values of the slice boundary-adjoining macro blocks already stored in the frame memory (40) are replaced. Thereby, the encoded picture data of arbitrary slice order can be completely decoded.
Inventors:
Toshihiko Kusakabe
Application Number:
JP2005009568A
Publication Date:
May 11, 2011
Filing Date:
January 17, 2005
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
H04N19/60; H03M7/36; H04N19/117; H04N19/136; H04N19/167; H04N19/423; H04N19/44; H04N19/503; H04N19/513; H04N19/80; H04N19/86; H04N19/91
Domestic Patent References:
| JP2000032297A |
Foreign References:
| WO2004008735A2 |
Other References:
Hae-Yong Kang et al.,MPEG4 AVC/H.264 decoder with scalable bus architecture and dual memory controller,Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on,IEEE,2004年 3月23日,Vol. 2,pp.145-148
Attorney, Agent or Firm:
Kazuyuki Hirano