Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP4711636
Kind Code:
B2
Abstract:
A drain diffusion layer 11 b includes a low impurity concentration region 5 a and a high impurity concentration region 5 b, and the low impurity concentration region 5 a is located on the channel region side. An impurity layer 7 having an opposite conductivity type to the drain diffusion layer 11 b is formed in the channel region, at a position away from the low impurity concentration region 5 a by a distance T. Alternatively, the low impurity concentration region 5 a and the impurity layer 7 are located so as to contact each other. Still alternatively, a border impurity layer is provided between the low impurity concentration region 5 a and the impurity layer 7 . Thus, a semiconductor device including a high voltage transistor capable of suppressing the reduction of the electric current driving capability and performing stable driving, and a method for fabricating the same, can be provided.
Inventors:
Mitsuhiro Suzuki
Morinaga Minoru
Masahiro Inoue
Morinaga Minoru
Masahiro Inoue
Application Number:
JP2004070784A
Publication Date:
June 29, 2011
Filing Date:
March 12, 2004
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
H01L29/78; H01L21/336; H01L21/8234; H01L29/76
Domestic Patent References:
| JP2001358334A | ||||
| JP200168560A | ||||
| JP200360199A | ||||
| JP1123416A | ||||
| JP1264262A | ||||
| JP6338616A | ||||
| JP7245410A | ||||
| JP818052A | ||||
| JP8236754A | ||||
| JP9223793A | ||||
| JP955502A | ||||
| JP62101074A |
Attorney, Agent or Firm:
Shiro Ogasawara
Kaoru Kuwahara
Takeji Takada
Kaoru Kuwahara
Takeji Takada