Title:
PLL回路のノイズを抑制するシステム及び方法
Document Type and Number:
Japanese Patent JP4754825
Kind Code:
B2
Abstract:
A system and method for improving the signal-to-noise ratio of a frequency generator suppresses phase noise and noise generated from mismatches in the internal generator circuits. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals maybe removed entirely or to any desired degree using, for example, a filter located along the signal path of the generator. In one embodiment, a Sigma-Delta modulator controls the value of a pulse-swallow frequency divider situated along a feedback path of a phase-locked loop to achieve a desired level of noise suppression. In another embodiment, a reference signal input into a phase-locked loop is modulated to effect noise suppression. In another embodiment, the foregoing forms of modulation are combined to accomplish the desired frequency shift. Through these modulation techniques, the signal-to-noise ratio of the frequency generator may be substantially improved while simultaneously achieving faster lock times.
Inventors:
An Yunho
Song Enseok
Ku ito
Lee Jung-Woo
Park Joan Flies
Lee Kyung Go
Song Enseok
Ku ito
Lee Jung-Woo
Park Joan Flies
Lee Kyung Go
Application Number:
JP2004548450A
Publication Date:
August 24, 2011
Filing Date:
October 23, 2003
Export Citation:
Assignee:
GTC Semiconductor Inc.
International Classes:
H03L7/197; H03L7/183
Domestic Patent References:
| JPH10247851A | 1998-09-14 | |||
| JPH10285027A | 1998-10-23 | |||
| JPH11195986A | 1999-07-21 | |||
| JP2003179490A | 2003-06-27 |
Foreign References:
| US20020145472A1 | 2002-10-10 |
Attorney, Agent or Firm:
Yoshikazu Tani
Kazuo Abe
Atsuhiro Hamanaka
Nobuyuki Kato
Kazuo Abe
Atsuhiro Hamanaka
Nobuyuki Kato