データ暗号化回路 - Renesas Electronics Corporation

Title:

データ暗号化回路

Document Type and Number:

Japanese Patent JP4761652

Kind Code:

B2

Abstract:

A data encryption circuit includes a plurality of buffers; an operation unit reading block data to be processed from any one of the buffers, executing an encryption or a decryption operation process, and writing the processed result into any one of the buffers; a data control unit writing block data to be processed into any one of the buffers and reading the operation result at the operation unit from any one of the buffers; and a buffer designating unit designating a buffer to be an object of input/output for the operation unit and data control unit, so as to prevent coincidence of a buffer into which data is read by the operation unit, a buffer into which data is written by the operation unit, a buffer into which data is read by the data control unit, and a buffer into which data is written by the data control unit.

Inventors:

Atsushi Yamaguchi

Application Number:

JP2001167780A

Publication Date:

August 31, 2011

Filing Date:

June 04, 2001

Export Citation:

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