Title:
不揮発性半導体記憶素子及びその製造方法並びに不揮発性半導体記憶素子を含む半導体集積回路装置
Document Type and Number:
Japanese Patent JP4761946
Kind Code:
B2
Abstract:
A non-volatile semiconductor memory element includes: a semiconductor region of a first conductivity type formed in a plate-like form on a semiconductor substrate; a first insulating film formed on a first side face of the semiconductor region; a first charge accumulating layer formed on a face of the first insulating film opposite from the semiconductor region; a second insulating film formed on a second side face of the semiconductor region, and has a different equivalent oxide thickness from the first insulating film; a second charge accumulating layer formed on a face of the second insulating film opposite from the semiconductor region; a third insulating film provided so as to cover the first and second charge accumulating layers; a control gate electrode provided so as to cover the third insulating film; a channel region formed in a portion of the semiconductor region covered with the control gate electrode; and source/drain regions of a second conductivity type formed in portions of the semiconductor region on both sides of the channel region.
Inventors:
Ono Rui Castle
Application Number:
JP2005337228A
Publication Date:
August 31, 2011
Filing Date:
November 22, 2005
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/8247; H01L21/8246; H01L27/10; H01L27/105; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP4302477A | ||||
| JP2005243709A | ||||
| JP10125810A | ||||
| JP2005057296A | ||||
| JP2004281782A |
Foreign References:
| US20030178670 |
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki